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EP CYCLING DEPENDENT ASYMMETRIC/SYMMETRIC VPASS CONVERSION IN NON-VOLATILE MEMORY STRUCTURES

2023
Online Patent
Zugriff:
Zum Volltext

A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprises determining a total number of erase/programming (EP) cycles that were applied previously to the memory cell and, (1) if the determined total number of cycles does not exceed a threshold value, applying an asymmetric programming scheme, and, (2) if the determined total number of cycles exceeds the threshold value, applying a symmetric programming scheme. Further, a magnitude of a boosting voltage bias (VPASS) that is to be applied to an unselected word line may be determined according to the determined total number of erase/programming (EP) cycles.

Titel:
EP CYCLING DEPENDENT ASYMMETRIC/SYMMETRIC VPASS CONVERSION IN NON-VOLATILE MEMORY STRUCTURES
Link:
Veröffentlichung: 2023
Medientyp: Patent
Sonstiges:
  • Nachgewiesen in: USPTO Patent Applications
  • Sprachen: English
  • Document Number: 20230282295
  • Publication Date: September 7, 2023
  • Appl. No: 17/685113
  • Application Filed: March 02, 2022
  • Assignees: SanDisk Technologies LLC (Addison, TX, US)
  • Claim: 1. A method for programming a target memory cell of a memory array of a non-volatile memory system, comprising: determining a total number of erase/programming (EP) cycles applied previously to the target memory cell; if the determined total number of erase/programming (EP) cycles does not exceed a threshold value, applying an asymmetric programming scheme; and if the determined total number of erase/programming (EP) cycles exceeds the threshold value, applying a symmetric programming scheme.
  • Claim: 2. The method according to claim 1, wherein the asymmetric programming scheme comprises: applying a programming voltage bias to a selected word line with respect to the target memory cell; applying a first boosting voltage bias (VPASS) to a first unselected word line; and applying a second boosting voltage bias (VPASS) to a second unselected word line, wherein: the second unselected word line is a last previously-programmed word line; and a magnitude of the second boosting voltage bias is less than a magnitude of the programming voltage bias and less than a magnitude of the first boosting voltage bias.
  • Claim: 3. The method according to claim 1, wherein the symmetric programming scheme comprises: applying a programming voltage bias to a selected word line with respect to the target memory cell; and applying a boosting voltage bias (VPASS) to one or more unselected word lines, wherein the magnitude of the boosting voltage bias is uniform with respect to each of the one or more unselected word lines.
  • Claim: 4. The method according to claim 1, wherein the threshold value is: pre-determined; and indicative of a near end-of-life condition of the target memory cell.
  • Claim: 5. The method according to claim 1, wherein the threshold value is: pre-determined; and indicative of a heavily cycled condition of the target memory cell.
  • Claim: 6. The method according to claim 1, wherein the memory array is a vertical three-dimensional NAND-type array.
  • Claim: 7. A non-volatile memory system, comprising: a memory array storing data in a target memory cell; and a memory controller coupled to the memory array and: determining a total number of erase/programming (EP) cycles applied previously to the target memory cell; if the determined total number of erase/programming (EP) cycles does not exceed a threshold value, applying an asymmetric programming scheme; and if the determined total number of erase/programming (EP) cycles exceeds the threshold value, applying a symmetric programming scheme.
  • Claim: 8. The non-volatile memory system according to claim 7, wherein the asymmetric programming scheme comprises: applying a programming voltage bias to a selected word line with respect to the target memory cell; applying a first boosting voltage bias (VPASS) to a first unselected word line; and applying a second boosting voltage bias (VPASS) to a second unselected word line, wherein: the second unselected word line is a last previously-programmed word line; and a magnitude of the second boosting voltage bias is less than a magnitude of the programming voltage bias and less than a magnitude of the first boosting voltage bias.
  • Claim: 9. The non-volatile memory system according to claim 7, wherein the symmetric programming scheme comprises: applying a programming voltage bias to a selected word line with respect to the target memory cell; and applying a boosting voltage bias (VPASS) to one or more unselected word lines, wherein the magnitude of the boosting voltage bias is uniform with respect to each of the one or more unselected word lines.
  • Claim: 10. The non-volatile memory system according to claim 7, wherein the threshold value is: pre-determined; and indicative of a near end-of-life condition of the target memory cell.
  • Claim: 11. The non-volatile memory system according to claim 7, wherein the threshold value is: pre-determined; and indicative of a heavily cycled condition of the target memory cell.
  • Claim: 12. The non-volatile memory system according to claim 7, wherein the memory array is a vertical three-dimensional NAND-type array.
  • Claim: 13. A method for programming a target memory cell of a memory array of a non-volatile memory system, comprising: determining a total number of erase/programming (EP) cycles applied previously to the target memory cell; and based upon the determined total number of erase/programming (EP) cycles, determining a magnitude of a boosting voltage bias (VPASS) to be applied to an unselected word line.
  • Claim: 14. The method according to claim 13, wherein the magnitude of the boosting voltage bias (VPASS) is determined using a lookup table stored at the non-volatile memory system.
  • Claim: 15. The method according to claim 14, wherein the lookup table comprises a series of different benchmark numbers of total erase/programming (EP) cycles, wherein each benchmark number in turn corresponds to a magnitude of the boosting voltage bias (VPASS).
  • Claim: 16. The method according to claim 14, wherein the lookup table comprises a succession of different benchmark numbers of total erase/programming (EP) cycles, and: each benchmark number in turn corresponds to a magnitude of the boosting voltage bias (VPASS); and the magnitude of the boosting voltage bias (VPASS) corresponding to a specific benchmark number is equal to, or greater than, the magnitude of the boosting voltage bias (VPASS) corresponding to the benchmark number immediately prior to the specific benchmark number in the succession.
  • Claim: 17. The method according to claim 14, wherein the lookup table comprises a succession of different benchmark numbers of total erase/programming (EP) cycles, and: each benchmark number in turn corresponds to a magnitude of the boosting voltage bias (VPASS); and the magnitude of the boosting voltage bias (VPASS) corresponding to a specific benchmark number differs from the magnitude of the boosting voltage bias (VPASS) corresponding to the benchmark number immediately prior to the specific benchmark number in the succession by a pre-determined voltage amount.
  • Claim: 18. The method according to claim 13, wherein the unselected word line is a last previously-programmed word line.
  • Claim: 19. The method according to claim 18, wherein: the unselected word line is: a first unselected word line; and a last previously-programmed word line; and a magnitude of a boosting voltage bias (VPASS) applied to any unselected word line other than the first unselected word line is unequal to the magnitude of the boosting voltage bias (VPASS) applied to the first unselected word line.
  • Claim: 20. The method according to claim 13, wherein the memory array is a vertical three-dimensional NAND-type array.
  • Current International Class: 11; 11; 11; 11; 11

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