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A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.

Titel:	FULLY PARAMETERIZABLE REPRESENTATION OF A HIGHER LEVEL DESIGN ENTITY
Autor/in / Beteiligte Person:	Boshart, Shawn ; Moinian, Shahriar ; Williams, Joshua ; Vuong, Hong-ha
Link:	Zum Volltext
Veröffentlichung:	2012
Medientyp:	Patent
Sonstiges:	Nachgewiesen in: USPTO Patent Applications Sprachen: English Document Number: 20120304140 Publication Date: November 29, 2012 Appl. No: 13/114834 Application Filed: May 24, 2011 Claim: 1. A parameterizable design system for use with semiconductor analog circuits, comprising: an interface unit connected to provide access to the system; a database unit connected to supply a library of parameterizable analog building blocks for a design entity; and a parameterization unit connected to select a parameter for one of the parameterizable analog building blocks of the library to meet a design specification of the design entity. Claim: 2. The system as recited in claim 1 further comprising a simulation unit connected to simulate an operation of the design entity employing the parameter. Claim: 3. The system as recited in claim 2 further comprising an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. Claim: 4. The system as recited in claim 1 wherein the parameter corresponds to a parameter set tailored for each of the library of parameterizable analog building blocks. Claim: 5. The system as recited in claim 1 wherein the parameter is selectable from a continuously variable range of parameter values to meet the design specification. Claim: 6. The system as recited in claim 1 wherein the parameter is selectable from a discretely variable range of parameter values to meet the design specification. Claim: 7. The system as recited in claim 1 wherein the library of parameterizable analog building blocks for a lowest design level corresponds to electronic symbols. Claim: 8. The system as recited in claim 1 wherein each representation of the design entity is parameterizable. Claim: 9. The system as recited in claim 1 wherein a representation of the design entity is selected from the group consisting of: an electronic symbol; an electronic schematic; a wiring netlist; and an electronic layout. Claim: 10. A method of designing a semiconductor analog circuit, comprising: providing a design specification; supplying a library of parameterizable analog building blocks for a design entity; and selecting, using a computer, a parameter for one of the parameterizable analog building blocks of the library for the design entity to meet the design specification. Claim: 11. The method as recited in claim 10 further comprising simulating an operation of the design entity employing the parameter. Claim: 12. The method as recited in claim 11 further comprising analyzing a sensitivity of the parameter for the design entity based on the design specification. Claim: 13. The method as recited in claim 10 wherein selecting the parameter corresponds to selecting from a parameter set tailored for each of the library of parameterizable analog building blocks. Claim: 14. The method as recited in claim 10 wherein selecting the parameter corresponds to selecting from a continuously variable range of parameter values to meet the design specification. Claim: 15. The method as recited in claim 10 wherein selecting the parameter corresponds to selecting from a discretely variable range of parameter values to meet the design specification. Claim: 16. The method as recited in claim 10 wherein the library of parameterizable analog building blocks for a lowest design level corresponds to electronic symbols. Claim: 17. The method as recited in claim 10 wherein each representation of the design entity is parameterizable. Claim: 18. The method as recited in claim 10 wherein a representation of the design entity is selected from the group consisting of: an electronic symbol; an electronic schematic; a wiring netlist; and an electronic layout. Current U.S. Class: 716/112 Current International Class: 06

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FULLY PARAMETERIZABLE REPRESENTATION OF A HIGHER LEVEL DESIGN ENTITY