Design and FPGA Implementation of High-Speed Area and Power Efficient 64-bit Modified Dual CLCG based Pseudo Random Bit Generator
In: IEEE International Symposium on Smart Electronic Systems (iSES); (2021-12-01) S. 93-98
Online
Konferenz
Zugriff:
Titel: |
Design and FPGA Implementation of High-Speed Area and Power Efficient 64-bit Modified Dual CLCG based Pseudo Random Bit Generator
|
---|---|
Autor/in / Beteiligte Person: | Ramapragada, Krishna Sai Tarun ; Netla, Ajith Kumar Reddy ; Chattada, Pavan Kalyan ; Manickam, Bhaskar |
Link: | |
Quelle: | IEEE International Symposium on Smart Electronic Systems (iSES); (2021-12-01) S. 93-98 |
Veröffentlichung: | 2021 |
Medientyp: | Konferenz |
ISBN: | 978-1-7281-8753-2 (print) |
DOI: | 10.1109/iSES52644.2021.00032 |
Sonstiges: |
|