A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 25 (2017-02-01), Heft 2, S. 714-724
Online
academicJournal
Zugriff:
Titel: |
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding
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Autor/in / Beteiligte Person: | Zhou, J. ; Zhou, D. ; Wang, S. ; Zhang, S. ; Yoshimura, T. ; Goto, S. |
Link: | |
Zeitschrift: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 25 (2017-02-01), Heft 2, S. 714-724 |
Veröffentlichung: | 2017 |
Medientyp: | academicJournal |
ISSN: | 1063-8210 (print) ; 1557-9999 (print) |
DOI: | 10.1109/TVLSI.2016.2593581 |
Sonstiges: |
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