Study of Pass-Gate Voltage (VPASS) Interference in Sub-30nm Charge-Trapping (CT) NAND Flash Devices
In: 3rd IEEE International Memory Workshop (IMW); (2011-05-01) S. 1-4
Online
Konferenz
Zugriff:
Titel: |
Study of Pass-Gate Voltage (VPASS) Interference in Sub-30nm Charge-Trapping (CT) NAND Flash Devices
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Autor/in / Beteiligte Person: | Hsiao, Yi-Hsuan ; Lue, Hang-Ting ; Chang, Kuo-Pin ; Hsieh, Chih-Chang ; Hsu, Tzu-Hsuan ; Hsieh, Kuang-Yeu ; Lu, Chih-Yuan |
Link: | |
Quelle: | 3rd IEEE International Memory Workshop (IMW); (2011-05-01) S. 1-4 |
Veröffentlichung: | 2011 |
Medientyp: | Konferenz |
ISBN: | 978-1-4577-0224-2 (print) ; 978-1-4577-0225-9 (print) ; 978-1-4577-0226-6 (print) |
ISSN: | 2159-483X (print) ; 2159-4864 (print) |
DOI: | 10.1109/IMW.2011.5873211 |
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