A PID SRF‐PLL based algorithm for positive‐sequence synchrophasor measurements.

Summary: Most of the proposed algorithms for synchrophasor estimation are based on the Discrete Fourier Transform (DFT). However, this technique has well‐known limitations, such as the leakage effect. Alternatively, this paper presents a positive‐sequence synchrophasor measurement algorithm based on a Synchronous Reference Frame Phase‐Locked Loop (SRF‐PLL). The algorithm is modular and consists of four stages. The first one is the abc‐dq transform that, with the aid of the second stage, a Finite Impulse Response (FIR) provides the positive‐sequence of the grid voltages. The filter also helps to improve the signal‐to‐noise ratio. This filter class was chosen due to its characteristic of linear phase and constant group delay to avoid unwanted phase distortions at the measurements. The third stage is an SRF‐PLL based on a PID controller that estimates the amplitude and phase of the grid voltage's positive‐sequence component and the grid frequency. By assessing the dynamic condition tests, it was observed that the PLL could not comply with all the IEEE standard requirements. Therefore, a fourth stage was included to calculate the frequency, and Rate of Change of Frequency (ROCOF) based on the estimated positive‐sequence phase. Experimental results obtained with a test platform shown that the proposed algorithm complies with all IEEE C37.118.1‐2011 and C37.118.1a‐2014 standard requirements. [ABSTRACT FROM AUTHOR]