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  1. Open detailed title display for 1
    Optimizing Multiplier Performance with Advanced PTL-Based AND Gate and Efficient Full Adder Design
    K, Paldurai ; M, Deepesh ; et al.
    In: 2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC), 2024-06-28, P. 295-300
    Online Conference
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    Ultra Low-Power Implementation of PTL based 1 -Bit Full Adder Using CNTFET Technology
    Singh, Priya ; Sharma, Uma
    In: 2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), Vol. 2 (2024-03-14), P. 1-5
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    PTL : The Rise and Fall of Jim and Tammy Faye Bakker's Evangelical Empire
    Wigger, John
    2017
    Online E-Book
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    Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style
    Pan, W. ; Yu, Y. ; et al.
    In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 71 (2024-07-01), Issue 7, P. 3538-3542
    Online Academic Journal
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    Design and Implementation of Power Efficient 8:1 Multiplexer using PTL Technology
    Agarwal, Sachin ; Pathak, Naveen ; et al.
    In: 2023 2nd International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS), 2023-04-05, P. 1-6
    Online Conference
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    Design and Optimization of 4-bit Absolute-value Comparator Using CMOS & PTL Technique
    Yu, Angquan ; Zhong, Yangchengzhen ; et al.
    In: 2021 International Conference on Electronic Information Engineering and Computer Science (EIECS), 2021-09-23, P. 912-916
    Online Conference
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    Performance Analysis of CMOS, PTL and GDI Based Braun Multiplier for Signal Processing Applications
    Basha, M. Mahaboob ; Gundala, Srinivasulu ; et al.
    In: 2021 International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT), 2021-08-27, P. 444-447
    Online Conference
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    PTL-AI Furnas Dataset: A Public Dataset for Fault Detection in Power Transmission Lines Using Aerial Images
    de Oliveira, Frederico Santos ; de Carvalho, Marcelo ; et al.
    In: 2022 35th SIBGRAPI Conference on Graphics, Patterns and Images (SIBGRAPI), Vol. 1 (2022-10-24), P. 7-12
    Online Conference
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    Comparative Analysis of LEAP and PTL techniques in 18nm FinFET Technology
    Rana, Gautam ; Sharma, Kulbhushan ; et al.
    In: 2023 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE), 2023-01-27, P. 788-790
    Online Conference
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    For licensing reasons this title can be displayed in the campus network only or after Login!
    Academic Journal
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    Academic Journal
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    Review of Power-to-Liquid (PtL) Technology for Renewable Methanol (e-MeOH): Recent Developments, Emerging Trends and Prospects for the Cement Plant Industry
    Marques, Luísa ; Vieira, Maria ; et al.
    In: Energies, Vol. 17 (2024-11-01), Issue 22, P. 5589
    Online Academic Journal
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    Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs
    Jha, Chandan ; Mekie, Joycee
    In: 2019 22nd Euromicro Conference on Digital System Design (DSD), 2019-08-01, P. 174-181
    Online Conference
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    For licensing reasons this title can be displayed in the campus network only or after Login!
    Academic Journal
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    Error Correctable Approximate Multiplier with Area/Power Efficient Design Through Mixed CMOS/PTL
    Arifeen, Tooba ; Hassan, Abdus Sami ; et al.
    In: 2018 21st Euromicro Conference on Digital System Design (DSD), 2018-08-01, P. 190-195
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    Bioforge PTL: An IoT Enabled Rapidly Deployable Phototherapy Device for Neonatal Jaundice
    Saha, Shovon Sudan ; Chowdhury, Hasib Ahmed ; et al.
    In: 2021 13th Biomedical Engineering International Conference (BMEiCON), 2021-11-19, P. 1-5
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    A Cascaded transition recurrent feature network (CTRFN) based Paramount Transfer learning (PTL) model for traffic congestion prediction
    Balasubramani, Karthika ; Natarajan, Umamaheswari
    In: Expert Systems With Applications, Vol. 248 (2024-08-15)
    Online Academic Journal
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    Design and Implementation of 2Bit Vedic Multiplier at 16nm Using PTL Logic
    Sharma, Kshitij ; Garg, Anubhav ; et al.
    In: 2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA), 2018-08-01, P. 1-5
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    Design & Performance Analysis of Low Power 1-bit Full Adder at 90 nm node using PTL Logic
    Das, Shibam Swarup ; Mishra, Ruby ; et al.
    In: 2018 Second International Conference on Computing Methodologies and Communication (ICCMC), 2018-02-01, P. 636-639
    Online Conference
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